Features inscribed into or provided through the surface of a semiconductor wafer or other microelectronic workpiece can serve a variety of functions. For example, a “via” or a “vertical interconnect access” is a through-chip feature that electrically couple terminals or other conductive elements on or proximate to one side of a wafer to conductive elements on or proximate to the other side of the wafer.
Typically, the formation of a via involves providing an opening in the microelectronic workpiece, i.e., in the wafer of semiconductor material. These openings can be manufactured in different ways, such as by using a dry-etch method or laser-drilling. Next, the wall or inner surface of the opening is electrically passivated by a layer of a dielectric, i.e., a non-conductive, material. This layer also serves as a seed layer enhancing adherence of other materials to the surface. Finally, the opening, which is now lined with the seed layer, is typically filled completely with a conductive material, such as a metal like copper, aluminum, tungsten or the like.
This approach, however, has certain drawbacks. First, the development of voids or cavities inside the conductive material caused by the shrinkage of the material during the solidification of the material cannot be completely prevented. Moreover, the mismatch of material properties such as the respective coefficients of thermal expansion (CTE) between the conductive material and the semiconductor substrate leads to different magnitudes of expansion as the microelectronic device or workpiece undergoes a temperature change. The mechanical stresses generated thereby may lead to cracks in and potentially a failure of the microelectronic device or workpiece.
Accordingly, a need exists for a through-chip feature that does not manifest these drawbacks. Furthermore a need exists for a method of forming such features.